Three dimensional (3-D) integration provides an effective platform for realizing improved circuits by integrating multiple layers of active devices on a single three dimensional chip. Three dimensional fabrication technologies can be broadly classified into two groups according to an integration scheme. The first technology is a three dimensional parallel integration scheme using through substrate via (TSV) based technology. Each active layer of the TSV based technology, along with respective interconnect metal layers, is fabricated separately and subsequently stacked using the through substrate vias to interconnect the active layers. The second technology is three dimensional monolithic integration, in which stacked active devices (e.g., transistors) are grown sequentially on the same substrate. In three dimensional (3-D) monolithic integration, a fabrication technology is selected to fabricate multiple layers of active-area (e.g., single crystal silicon (Si) or recrystallized poly-silicon) that are separated by interlayer dielectrics (ILDs) for 3-D circuit processing.
FIG. 1 illustrates a cross sectional view of a three dimensional monolithic die 100 with two active layers 102 and 104. In the three dimensional monolithic die 100, a second active layer 104 is fabricated on a first active layer 102. The second active layer 104, which includes P-MOS transistors 130, is aligned on top of the first active layer 102, which includes N-MOS transistors 120. The N-MOS transistors 120 are fabricated on a first silicon on insulator layer (SOI-1) 122, and the P-MOS transistors 130 are fabricated on a second silicon on insulator layer (SOI-2) 132.
The first active layer 102 and the second active layer 104 are sequentially grown on a silicon substrate 106. In particular, silicon epitaxial growth (SEG) is used to grow silicon crystal vertically and laterally to cover an interlayer dielectric (e.g., a first insulator layer 108 of silicon dioxide (SiO2)) on the silicon substrate 106. Devices (e.g., N-MOS transistors 120) within the first active layer 102 are fabricated on the grown layer 122. A second insulator layer 110 of SiO2 is deposited on the first active layer 102. Silicon epitaxial growth then grows another silicon on insulator layer (SOI-2) 132 on the second insulator 110. The devices (e.g., P-MOS transistors 130) within the second active layer 104 can be fabricated on the second silicon on insulator layer (SOI-2) 132 on top of the second insulator layer 110. Additional active layers may be fabricated above the second, active layer 104 using silicon epitaxial growth.
Currently, materials for 3-D monolithic integration include silicon and germanium. FIGS. 2-3 illustrate a conventional crystallized silicon layer transfer process flow. A wafer (or die) 302, including underlying CMOS (complementary metal oxide semiconductor) circuitry 320, is provided. The CMOS circuitry 320 may include device transistors 321 and conductive (e.g., metal) interconnects (such as a via layer 322 and a horizontal metal layer 323). Although only a single layer of vias 322 and a single horizontal layer 323 are shown, it is appreciated that multiple such layers exist.
An oxide layer 304 is deposited on top of the CMOS circuitry 320 of the wafer 302. A cleavable wafer 306 is then bonded onto the wafer 302 with an oxide-oxide bonding process. The cleavable wafer 306 includes a cut layer 308, a semiconductor layer 310, and an oxide layer 316. The semiconductor layer 310 may be a crystallized silicon the subsequently constructing transistors.
As seen in FIG. 3, after oxide-oxide bonding of the two wafers 302 and 306, a cutting step is performed to cleave and remove a top portion 312 of the cleavable wafer 306 along the cut layer 308. The result is a three dimensional wafer 314 that includes the wafer 302 with the crystallized silicon layer 310. An additional process may be performed to provide electrical connections (e.g., vertical vias) between any devices fabricated within the crystallized silicon layer 310 and the device transistors of the CMOS circuitry 320.
Fabrication of devices (e.g., transistors) in the crystallized silicon layer 310, however, is limited. Although this limitation is discussed generally with reference to silicon wafers, the limitation exists in conventional silicon CMOS process flows that involve ion-implants and activations. In particular, high temperatures are specified for fabricating devices in the crystallized silicon layer 310. Such high temperatures, however, damage the existing circuits 320 on the wafer 302. For example, the back end of line (BEOL) components (e.g., vias 322 and interconnecting metal lines 323 of the CMOS devices 320) would likely melt at the temperatures specified to fabricate devices in the crystallized silicon layer 310. That is, the high temperatures involved in silicon epitaxial growth cause significant degradation to the devices (e.g., N-MOS transistors 120) on lower layers (e.g., first active layer 102), as shown in FIG. 1.
To avoid the excessive heat specified for fabricating devices in the crystallized silicon layer 310, a lower quality material, such as polysilicon, is used for fabricating transistors in the crystallized silicon layer 310. For example, as shown in FIG. 1, a single crystal 124 is used in the fabrication of the N-MOS transistors 120. The use of a single crystal 124 provides improved electron mobility within the N-MOS transistors 120 to optimize the performance of the N-MOS transistors 120. The P-MOS transistors 130, however, are fabricated using a polysilicon 134 because such fabrication can be performed at a lower temperature that does not damage the BEOL components 323. Unfortunately, the P-MOS transistors 130 are not optimized for performance because polysilicon 134 exhibits reduced electron mobility as compared to the single crystal 124.